1. Field of the Invention
The present invention generally relates to a memory device, and particularly relates to a nonvolatile memory device which is capable of retaining stored data in the absence of a power supply voltage.
2. Description of the Related Art
Nonvolatile semiconductor memory devices, which can retain stored data even when power is turned off, include flash EEPROMs employing a floating gate structure, FeRAMs employing a ferroelectric film, MRAMs employing a ferromagnetic film, etc.
In the case of EEPROMs, there is a need to manufacture a transistor having a special structure comprised of a floating gate. In the case of FeRAMs and MRAMs, which achieve nonvolatile storage by use of a ferroelectric material and a ferromagnetic material, respectively, there is a need to form and process a film made of these respective materials. The need for such transistor having a special structure and the need for such film made of a special material are one of the factors that result in an increase in the manufacturing costs.
PCT/JP2003/016143, which was filed on Dec. 17, 2003, the entire contents of which are hereby incorporated by reference, discloses a nonvolatile memory cell (i.e., a basic unit of data storage) comprised of a pair of MIS (metal-insulating film-semiconductor) transistors that have the same structure as ordinary MIS transistors used for conventional transistor functions (e.g., switching function). Namely, these memory cell transistors use neither a special structure such as a floating gate nor a special material such as a ferroelectric material or a ferromagnetic material. These MIS transistors are configured to experience an irreversible hot-carrier effect on purpose for storage of one-bit data.
The hot-carrier effect leaves an irreversible lingering change in the transistor characteristics such as the threshold or on-resistance of the transistors. Changes in the characteristics of the MIS transistors caused by the hot-carrier effect achieve nonvolatile data retention. Which one of the MIS transistors has a stronger lingering change determines whether the stored data is “0” or “1”.
A latch (flip-flop) circuit may be used together with the pair of MIS transistors for the purpose of reading (sensing) the data stored in the pair of MIS transistors. Such latch circuit may also be used to determine data to be stored in the memory-cell MIS transistors. That is, data to be stored as nonvolatile data may be first set in the latch circuit, and, then, the data stored in the latch circuit may subsequently be stored in the pair of MIS transistors. The latch circuit and the memory-cell MIS transistors together constitute a memory cell (memory circuit).
When a nonvolatile memory device having the nonvolatile memory cells as described above is manufactured, there is a need to conduct a test to ensure that the memory cells perform properly as designed. The latch circuit portion of each memory cell may properly be tested by use of a conventional SRAM test. The nonvolatile memory portion (comprised of a pair of memory-cell MIS transistors) of each memory cell, however, cannot be tested by use of a conventional test technique. This is because the operation of the nonvolatile memory portion is founded on an irreversible change of the transistor characteristics. If a test that creates such an irreversible change is actually performed, the memory circuit may no longer be usable.
Accordingly, there is a need for a nonvolatile memory device provided with a test mechanism that can test the operation of the memory cells without undermining the function of the memory cells where the memory cells include MIS transistors that are designed to experience an irreversible change in their characteristics for the purpose of nonvolatile data retention.